1. Field of the Invention
The present invention relates generally to semiconductor devices and integrated circuits and, more particularly, to a method of and system for reducing the drive requirements for the input and output pads of an integrated circuit die.
2. Description of the Related Technology
Integrated circuits have revolutionized the field of electronics by making possible a level of technological sophistication unknown in the days of vacuum tubes and even discrete transistors. An integrated circuit may comprise, on a small silicon chip, many thousand or even a million or more transistors, including associated diodes, resistors and capacitors, interconnected together to form complex electronic functions. The integrated circuit chip or "die" is packaged in an encapsulating package having leads or "pins" for connecting the integrated circuit functions to the overall electronic system or product incorporating a plurality of integrated circuits.
Semiconductor integrated circuits comprise the majority of electronic circuits in computers and other digital electronic products. Present technology integrated circuits may contain millions of transistors and be configured, for example, as a central processing unit (CPU), arithmetic logic unit (ALU), random access memory (RAM), programmable logic array (PLA), application specific integrated circuit (ASIC), or digital signal processor (DSP). Both sophistication and speed of operation of these integrated circuits has rapidly increased because of improvements in integrated circuit manufacturing technologies resulting in smaller and faster devices.
Semiconductor integrated circuits may be formed on silicon wafer chip dies by a plurality of layers of different materials. These materials are selected for their conduction, insulation or electron charge characteristics. Transistors may be formed into the silicon die by diffusion means well known to those skilled in the art of fabricating integrated circuit dies.
Layers of insulating oxides may be deposited over selected areas of the integrated circuit die so that conductive layers of polysilicon or metal may be deposited thereon. Various methods of deposition may be utilized such as, for example, chemical vapor deposition (CVD) or other methods well known to those skilled in the art of fabricating integrated circuits. Polysilicon may be used as both a circuit element and a conductor such as, for example, the gate structure in a metal oxide semiconductor field effect transistor (MOSFET). Metal is used for interconnection between various circuit elements and for connection to the integrated circuit connection pads.
Connections from the integrated circuit die are generally made by means of the connection pads. The connection pads are located on the face of the integrated circuit die. Bond wires connect the pads to a lead frame which becomes the pins of the integrated circuit package that connect to the electronic system.
These connection pads on the face of the integrated circuit die may be about 60 to 100 micrometers on a side and may be substantially square. The connection pad is mostly parallel with the face of the die and the pad may have a thickness of about from 0.7 to 1 micrometer. Generally, there are one or more insulating layers between the metal connection pad and the surface of the silicon wafer die or "substrate" face. There may also be one or more additional layers of metal and/or polysilicon between the substrate and the connection pad.
The connection pad surface and substrate form a capacitor wherein the pad is the positively charged plate at a logic high level, typically V.sub.dd, the substrate is the negatively charged plate at V.sub.ss, and intervening insulation therebetween is the dielectric. Typically, capacitance associated with a connection pad is about 0.5 to 1 picofarad (pF). The pad capacitance is added to the capacitance of the integrated circuit package and electronic system circuit board. The package and system circuit capacitance may be about 5 pF per connection. Thus, the connection pad adds a significant amount of capacitance to the overall system capacitance per connection.
Any circuit capacitance must be charged when going from a low to high logic state, and discharged when going from a high to low logic state. Charging of the circuit capacitance is performed by an output driver circuit such as, for example, a complementary metal oxide semiconductor (CMOS) transistor amplifier. A CMOS output driver, however, must be designed with electrostatic discharge (ESD) protection in mind. The design rules for CMOS ESD protection restrict the CMOS driver performance, including the current drive capability needed to charge and discharge output circuit capacitance.
Inputs to the integrated circuit die also utilize connection pads similar to the output pads described above. When an input is connected to an output, the input capacitance adds to the overall circuit connection capacitance. Input capacitance may be about 0.5 to 1 pF. This amount of input capacitance is significant and represents the majority of the connected capacitance, especially when multiple integrated circuit dice are connected in a hybrid package utilizing close coupled wire bonding therebetween.
Since CMOS transistor amplifier capacitive drive capabilities are limited because of ESD design constraints, what is needed is a way of reducing the output capacitance charge requirements, and, preferably, the input capacitance charge requirements caused by the connection pad capacitance of the integrated circuit die. By reducing overall connection capacitance charging requirements, smaller driver transistors may be utilized in the output amplifiers of the integrated circuit. Use of small transistors results in a smaller integrated circuit die or the capability of having more transistor functions on a given die size.